PPABench — Accelerator Chassis Templates

Six accelerator IPs in the locked Caravel user_project_wrapper, each driven at real chip pins by a harness VIP and graded by an independent open-source oracle.

Harness VIP (BFM) Caravel wrapper (fixed chassis) Accelerator IP (the design) QSPI-ROM VIP BT.656 video VIP Independent oracle

The model. An MCU offloads work to an accelerator over real pin-level buses — no AXI-Stream (that's on-chip fabric, not chip I/O). The host is a QSPI master (qspi_host.py); bulk data uses a dedicated port: BT.656 for video-in, a QSPI-master ROM read for DSP operands. The GPIO pin map is shared: io[0] csn, io[1] sck, io[5:2] quad IO, io[7] bt656_pclk, io[15:8] bt656_d, io[16/17] rom_csn/sck, io[21:18] rom_io. Every accelerator implements a QSPI-slave FSM with a real SCK→core-clock CDC.

Repo balbekov/ppabench · chassis/accel/. PPA = yosys sky130_fd_sc_hd (tt, 25 °C, 1v8), top = user_project_wrapper. Each acceptance oracle is an independent open-source tool that never saw the RTL — see VALIDATION.md.